Military

MathWorks debuts HDL code generation, verification across MATLAB, Simulink for FPGA, ASIC, high-integrity, and standards-compliant designs

NATICK, Mass., 12 March 2012. MathWorks has unveiled HDL Coder, its new product that automatically generates HDL code from MATLAB, and HDL Verifier, which offers FPGA hardware-in-the-loop capabilities ...
Engineering

Verify FPGA and ASIC Video Streaming Capabilities on MATLAB or Simulink

MathWorks has released the Vision HDL Toolbox, a library of image processing and computer vision algorithms designed for field-programmable gate arrays (FPGA) and application-specific integrated ...
Business Wire

MathWorks Speeds Up FPGA-in-the-Loop Verification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with ...
EDN

FPGA design and verification using Simulink

Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ...