A new technical paper titled “Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding” was published by researchers at National Chung Hsing University (NCHU) and Osaka University.

Make large-scale simulations smarter and faster, up to 300X faster in some cases, for an improved return on software, hardware, human resources, and other investments.

Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology.” Abstract “Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to ...

The small and complicated features of TSVs give rise to different defect types. Defects can form during any of the TSV ...

In today’s advanced packages, however, resistance no longer resides primarily inside transistors or neatly bounded test ...

For decades, optical inspection has been the primary method for process control in fabs. However, the move to multi-level ...

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...

The shift to multi-die assemblies is forcing changes in how chips are tested and inspected in order to achieve sufficient yield ramp or respond more quickly to yield excursions.

Researchers from Rice University, University of Utah and National University of Singapore (NUS) published “Three-dimensional ...

The critical role of mechanical stress in FinFET performance and the importance of pitch control to minimize variability and optimize device parametric targets.

Researchers from Fudan University designed a fiber integrated circuit (FIC) with a multilayered spiral architecture. The ...

Data center AI is driving a dramatic ramp in the growth of silicon photonics foundries: 8X growth in just 6 years, from 2026 to 2032. Scale-out is the major driver now. Scale-up will become the ...