PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace. According to the “PCI ...

This collaboration highlights GUC's commitment to deliver comprehensive and innovative design solutions, enabling customers ...

This funding will support the continued development and demonstration of Strategic Radiation Hardened (SRH) high reliability ...

The partnership between Silvaco and Micon Global is expected to drive Silvaco’s expansion across the EMEA market, leveraging Micon Global’s expertise to enhance client access to Silvaco’s design ...

The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router, controllers, PHYs with support for the USB ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Proven Single Port SRAM compiler for GF55 LPx - Memory optimized for ultra high density and high speed with compiler range up to 320K bits ...

Microtronix began as a design and embedded engineering firm for custom networking equipment for the Telco marketplace, pioneering the X25 protocol. Today, Microtronix uses these same engineering ...

The 10/100/1G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1000M Ethernet ...

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ... Rambus ...

The G_999_1 Verification IP is compliant with ITU-T G.999.1 specifications and verifies MAC-to-PHY interfaces of designs with a 1G Ethernet interface GMII/GMII TBI. It can work with SystemVerilog,Vera ...